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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4041B buffers Quadruple true/complement buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple true/complement buffer DESCRIPTION The HEF4041B is a quadruple true/complement buffer which provides both an inverted active LOW output (O) and a non-inverted active HIGH output (O) for each input (I). The buffers exhibit high current output capability suitable for driving TTL or high capacitive loads. HEF4041B buffers Fig.2 Pinning diagram. HEF4041BP(N): HEF4041BD(F): HEF4041BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one buffer). APPLICATION INFORMATION Some examples of applications for the HEF4041B are: * LOCMOS to DTL/TTL converter * High current sink and source driver Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification Quadruple true/complement buffer DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (C) VDD V Output (source) current HIGH HIGH Output (sink) current LOW 5 10 15 5 4,75 10 15 VOH V 4,6 9,5 13,5 2,5 0,4 0,5 1,5 IOL -IOH -IOH VOL V SYMBOL -40 +25 HEF4041B buffers +85 MIN. 1,0 2,7 10,0 3,0 1,35 4,5 15,0 MAX. mA mA mA mA mA mA mA MIN. MAX. MIN. TYP. 1,6 4,5 16,0 5,0 2,0 7,5 23,0 1,3 3,6 14,0 4,0 1,7 6,0 20,0 2,6 7,0 30,0 8,0 4,0 12,0 35,0 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH In On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times On On HIGH to LOW LOW to HIGH 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL tPLH tPHL 30 20 15 30 15 10 35 20 15 35 20 15 25 12 8 25 12 8 65 40 30 55 30 20 75 40 30 75 40 30 50 25 20 45 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 ns + (0,27 ns/pF) CL 14 ns + (0,11 ns/pF) CL 12 ns + (0,08 ns/pF) CL 17 ns + (0,27 ns/pF) CL 9 ns + (0,11 ns/pF) CL 7 ns + (0,08 ns/pF) CL 22 ns + (0,27 ns/pF) CL 14 ns + (0,11 ns/pF) CL 12 ns + (0,08 ns/pF) CL 22 ns + (0,27 ns/pF) CL 14 ns + (0,11 ns/pF) CL 12 ns + (0,08 ns/pF) CL 5 ns + (0,40 ns/pF) CL 2 ns + (0,21 ns/pF) CL 1 ns + (0,14 ns/pF) CL 5 ns + (0,40 ns/pF) CL 2 ns + (0,21 ns/pF) CL 1 ns + (0,14 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 3 Philips Semiconductors Product specification Quadruple true/complement buffer HEF4041B buffers VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 3100 fi + (foCL) x VDD2 12 700 fi + (foCL) x 33 800 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 |
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